1. What is the difference between a latch and a flip flop. For the same input, how would the output look for a latch and for a flip-flop.
2. Finite state machines:
(2.1)Design a state-machine (or draw a state-diagram) to give an output '1' when the # of A's are even and # of B's are odd. The input is in the form of a serial-stream (one-bit per clock cycle). The inputs could be of the type A, B or C. At any given clock cycle, the output is a '1', provided the # of A's are even and # of B's are odd. At any given clock cycle, the output is a '0', if the above condition is not satisfied.
(2.2). To detect the sequence "abca" when the inputs can be a b c d.
3. minimize a boolean expression.
4. Draw transistor level nand gate.
5. Draw the cross-section of a CMOS inverter.
6. Deriving the vectors for the stuck at 0 and stuck at 1 faults.
7. Given a boolean expression he asked me to implement just with muxes but nothing else.
8. Draw Id Vds curves for mosfets and explain different regions.
9. Given the transfer characteristics of a black box draw the circuit for the black box.
10. Given a circuit and its inputs draw the outputs exact to the timing.
11. Given an inverter with a particular timing derive an inverter using the previous one but with the required timing other than the previous one.
12. Change the rise time and fall time of a given circuit by not changing the transistor sizes but by using current mirrors. 13. Some problems on clamping diodes.
2. Finite state machines:
(2.1)Design a state-machine (or draw a state-diagram) to give an output '1' when the # of A's are even and # of B's are odd. The input is in the form of a serial-stream (one-bit per clock cycle). The inputs could be of the type A, B or C. At any given clock cycle, the output is a '1', provided the # of A's are even and # of B's are odd. At any given clock cycle, the output is a '0', if the above condition is not satisfied.
(2.2). To detect the sequence "abca" when the inputs can be a b c d.
3. minimize a boolean expression.
4. Draw transistor level nand gate.
5. Draw the cross-section of a CMOS inverter.
6. Deriving the vectors for the stuck at 0 and stuck at 1 faults.
7. Given a boolean expression he asked me to implement just with muxes but nothing else.
8. Draw Id Vds curves for mosfets and explain different regions.
9. Given the transfer characteristics of a black box draw the circuit for the black box.
10. Given a circuit and its inputs draw the outputs exact to the timing.
11. Given an inverter with a particular timing derive an inverter using the previous one but with the required timing other than the previous one.
12. Change the rise time and fall time of a given circuit by not changing the transistor sizes but by using current mirrors. 13. Some problems on clamping diodes.
Logic design:
1. Draw the transistor level CMOS #input NAND or NOR gate.After drawing it lot of qestions on that ckt will be asked.
2. Transistor sizing for given rise time and fall time. How do you size it for equal rise and fall time.
3. Given a function whose inputs are dependent on its outputs. Design a sequential circuit.
4. Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1.
5. Given a boolean equation minimize it.
6. Given a boolean equation draw the transistor level minimum transistor circuit.
7. What is the function of a D-flipflop, whose inverted outputs are connected to its input ?
8. What will you do if you want to drive a large capacitance ?
Computer Architecture Questions:
1. Explain what is DMA?
2. what is pipelining?
3. what are superscalar machines and vliw machines?
4. what is cache?
5. what is cache coherency and how is it eliminated?
6. what is write back and write through caches?
7. what are different pipelining hazards and how are they eliminated.
8. what are different stages of a pipe?
9. eplain more about branch prediction in controlling the control hazards
10. Give examples of data hazards with pseudo codes.
11. Caluculating the number of sets given its way and size in a cache?
12. How is a block found in a cache?
13. scoreboard analysis.
14. What is miss penalty and give your own ideas to eliminate it.
15. How do you improve the cache performance.
16. Different addressing modes.
17. Computer arithmetic with two's complements.
18. About hardware and software interrupts.
19. What is bus contention and how do you eliminate it.
20. What is aliasing?
21) What is the difference between a latch and a flip flop?
22) What is the race around condition? How can it be overcome?
23) What is the purpose of cache? How is it used?
24) What are the types of memory management
2. what is pipelining?
3. what are superscalar machines and vliw machines?
4. what is cache?
5. what is cache coherency and how is it eliminated?
6. what is write back and write through caches?
7. what are different pipelining hazards and how are they eliminated.
8. what are different stages of a pipe?
9. eplain more about branch prediction in controlling the control hazards
10. Give examples of data hazards with pseudo codes.
11. Caluculating the number of sets given its way and size in a cache?
12. How is a block found in a cache?
13. scoreboard analysis.
14. What is miss penalty and give your own ideas to eliminate it.
15. How do you improve the cache performance.
16. Different addressing modes.
17. Computer arithmetic with two's complements.
18. About hardware and software interrupts.
19. What is bus contention and how do you eliminate it.
20. What is aliasing?
21) What is the difference between a latch and a flip flop?
22) What is the race around condition? How can it be overcome?
23) What is the purpose of cache? How is it used?
24) What are the types of memory management
COMPUTER ARCHITECTURE QUESTIONS
1. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
2. Explain the operation considering a two processor computer system with a cache for each processor.
What are the main issues associated with multiprocessor caches and how might you solve it?
What are the main issues associated with multiprocessor caches and how might you solve it?
3. Explain the difference between write through and write back cache.
4. Are you familiar with the term MESI?
5. Are you familiar with the term snooping?
STATE MACHINE QUESTIONS
1. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
2. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
SIGNAL LINE QUESTIONS
1. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot,
undershoot or signal threshold violations, what can be done to correct this problem?
undershoot or signal threshold violations, what can be done to correct this problem?
VALIDATION QUESTIONS:
What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++?
What compiler was used?
Have you studied busses? What types?
Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
How many bit combinations are there in a byte?
What is the difference between = and == in C?
Are you familiar with VHDL and/or Verilog?
MEMORY, I/O, CLOCK AND POWER QUESTIONS
1. What types of CMOS memories have you designed? What were their size? Speed? Configuration Process technology?
2. What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?
3. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Process technology? What package was used and how did you model the package/system?
What parasitic effects were considered?
4. What types of high speed CMOS circuits have you designed?
5. What transistor level design tools are you proficient with? What types of designs were they used on?
6. What products have you designed which have entered high volume production?
What was your role in the silicon evaluation/product ramp? What tools did you use?
7. If not into production, how far did you follow the design and why did not you see it into production
